The present invention relates to a clock generator for producing nonoverlapping clock signals.
A large number of logic circuits including shift registers require two-phase clock signals to control their various operations. Two-phase clock signals are clock or timing signals in which the high and low levels are nominally 180.degree. out of phase. To ensure that no logical errors occur in the operation of the logic circuit the two-phase clock signals must be nonoverlapping, that is, one must be high when the other is low and vice versa; the two clock signals should not be both high (or low) at the same time. It is also advantageous, particularly when the clock generator is implemented in the form of an MOS LSI integrated circuit, for the two-phase clock generator to consume a minimum amount of power and to employ a minimum number of devices so as to reduce the amount of chip area required to implement the circuit.
In one presently known clock generator, the input clock is applied to an input of a depletion-mode MOS device, the output of which constitutes one of the clocks. The input clock is also applied to the input of an inverter, which produces the other clock at its output. It has been found that as a result of the relatively high capacitance of the output of the depletion-mode MOS device in this prior art circuit, the fall time of the lagging edge of the clock is relatively long, which creates the likelihood of a degree of overlap between the two clocks that could, in turn, result in unacceptable errors in the logic operations controlled by these clocks.